The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the electronic design methodologies. In modern electronic circuits, the total number of transistors has increased; geometries have become smaller; and clock frequencies have increased over time. Errors on silicon have become prohibitively expensive. To address the challenges arising out of the ever increasing total number of transistors and clock frequencies, huge amount of efforts in electronic designs have been devoted to post-layout optimization and analyses that attempt to identify such errors and to fix these errors to reduce mask manufacturing errors and mask manufacturing cycle time.
Nonetheless, the number of transistors may easily exceed 100 million per square millimeter, and the total number of transistors is in the order of tens of billions in a modern integrated circuit (IC) as of the year 2017. The sheer number of transistors and hence the complexity of a modern electronic design simply requires a long runtime for any analyses to generate useful results, much less accurate result. Furthermore, parasitic effects and therefore their resulting impacts (e.g., Ohm heating, electro-migration, etc.) can no longer be ignored in the highly dense modern electronic designs. Accounting for such parasitic effects further imposes a tremendous burden on post-layout optimizers, simulators, and analyzers and hence exacerbates these challenges.
Some conventional approaches attempt to tackle such challenges by using brute force approaches in modern optimizers, simulators, and analyzers. Such conventional approaches simply require prohibitively long runtime and computational resources. Certain conventional approaches attempt to improve the computational resource utilization by applying circuit reduction techniques to reduce the size and complexity of an electronic design. Nonetheless, these conventional approaches apply a reduction technique to the entire electronic design and thus fall short due to the pessimism or optimism of the reduction technique. For example, a conservative reduction technique falls short because the limited reduction of the electronic design merely marginally improves the runtime of the post-layout optimizers, analyzers, or simulators. On the other hand, an aggressive reduction technique falls short by reducing the electronic design with an overly aggressive technique and thus fails to produce sufficiently accurate results or coverage.
Therefore, it is important for an EDA tool to more efficiently, effectively, and accurately implement electronic designs with hybrid analysis techniques described below to address at least the aforementioned shortcomings of conventional approaches.